搜索资源列表
uvm
- the Universal Verification Methodology (UVM) for creating SystemVerilog testbenches.
uvm-1.1d.tar
- UVM World 官方发布的UVM（通用验证方法学）的源代码，基于SystemVerilog，用于ASIC Verification。2013-03最新发布版本uvm-1.1d.tar.gz-The UVM World official release of the source code of the UVM (Universal Verification Methodology), based on SystemVerilog for ASIC Verification. 2013-03
uvm
- UVM验证平台的介绍，在验证方面效率由于systemverilog。-UVM verification platform introduced in verification efficiency due systemverilog.
UVM_Golden_Reference_Guide
- The UVM Golden Reference Guide is a compact reference guide to the Universal Verification Methodology for SystemVerilog. it offers answers to the questions most often asked during the practical application of UVM in a convenient and concise ref
UVM_Class_Reference_Manual_1.2
- The UVM Class Library provides the building blocks needed to quickly develop wellconstructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each us
uart2bus_testbench_latest.tar
- uart2bus_testbench,uart测试平台，主要运用uvm验证方法学，对uart接口、systemverilog和uvm等ic开发和验证有一个初步了解和掌握。-Uart2bus_testbench, uart test platform, the main use of uvm validation methodology, uart interface, systemverilog and uvm ic development and verification have a pre
Universal_Verification_Methodology
- The universal verification Methodlology is a complete mothodology that codifies the best practices for efficient and exhaustive verification.
Universal_Verification_Methodology_examples
- a practical guide to adopting the universal verification methodology examples The universal verification Methodlology is a complete mothodology that codifies the best practices for efficient and exhaustive verification.
THE_UVM_PRIMER_CODE_EXAMPLES.tar
- The exmaples for the ebook The UVM Primer An Introduction to the Universal Verification Methodology by Ray Salemi The UVM Primer is the book to read when you've decided to learn the UVM. The book assumes that you have a basic knowledge of SystemVeri
UVM_GetStart
- From OVM to UVM UVM is based on OVM, so from the outset it should be very straightforward to interoperate between OVM and UVM or to convert old OVM code to UVM code. We thought we would test this out by converting our existing online tutorial Getti
UVM1.1应用指南及源代码分析_20111211版.pdf
- 该书用来介绍UVM的架构，语法，包含很多示例，适用于初学者(The book used to introduce the UVM architecture, syntax, including many examples, for beginners)
uvm-cookbook-complete-verification-academy
- UVM cookbook from mentors
uvm实战源码
- uvm实战教程源码，丰富的uvm demo testbench,可以学习uvm各个阶段的testbench搭建技巧，能学习到大量的uvm testbench搭建技能，比如factory和寄存器模型等重要机制，非常值得学习
AHB2-master
- AMBA AHB 2.0 VIP in SystemVerilog UVM
AHB5-master
- amba ahb2 协议vip，包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)